A Modified Clock Scheme for a Low Power BIST Test Pattern Generator

In this paper, we present a new low power BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. Numerous advantages can be found in applying such a technique. The fault coverage and the test time are roughly the same as those achieved using a standard BIST scheme. The area overhead is nearly negligible and there is no penalty on the circuit delay. The proposed BIST scheme does not require any circuit design modification beyond the parallel BIST technique, is easily implemented and has low impact on the design time. It has been implemented based on an LFSR-based TPG, but can also be designed using a cellular automata. Reductions of the energy, average power and peak power consumption during test operation are up to 94%, 55% and 48% respectively for ISCAS and MCNC benchmark circuits. List of keywords : Parallel BIST, Low-power Design, Test & Low Power, Low Power BIST Suggested topic: Built-in Self-Test (BIST) • Corresponding Author: Dr. Patrick GIRARD Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier, Université Montpellier II / CNRS 161 rue Ada, 34392 Montpellier Cedex 5 FRANCE Tél. : (+33) 467 41 86 29 Fax : (+33) 467 41 85 00 Email : [email protected] Proposed to IEEE VLSI Test Symposium April 29 May 3, 2001